1 |
2024 |
Design and Linearity Analysis of a Dual Control 5-Stage CSR-VCO for RF Applications |
Md. Anwarul Abedin, Khaled Hasan, Sidrat Muntaha Nur Pranto and Sudipta Chakraborty |
International Conference on Advancement in Electrical and Electronic Engineering |
2 |
2024 |
Optimization of Different III-V Multiple Quantum Well Solar Cells with Surficial Circular Nanoholes |
M. Kamruzzaman and M. A. Abedin |
International Conference on Advancement in Electrical and Electronic Engineering |
3 |
2023 |
Design of Pass Transistor-Based Low-Power Approximate Adders for DSP Application |
Khaled Hasan, Sidrat Muntaha Nur Pranto, Shuvankar Biswas, Fajla Rabby, Md. Atiqur Rahman and Md. Anwarul Abedin |
26th International Conference on Computer and Information Technology (ICCIT), 2023 |
4 |
2022 |
FPGA Implementation of Multiple Single Phase PWM Inverters with Configurable Duty Cycle and Dead Time |
M. S. Rana, M. Bepari, K. Ghosh and M. A. Abedin |
International Conference on Advancement in Electrical and Electronic Engineering |
5 |
2022 |
Design of Octonary Memory Cell using Memristor-MOS Hybrid Structure |
B. C. Biswas and M. A. Abedin |
International Conference on Advancement in Electrical and Electronic Engineering |
6 |
2019 |
Implementation of an XOR based 16-bit Carry Select Adder for Area, Delay and Power Minimization |
A. N. M. Hossain and M. A. Abedin |
International Conference on Electrical, Computer Communication Engineering (ECCE 2019), 07-09 February 2019, Cox’s Bazar, Bangladesh. |
7 |
2018 |
Development of Simulation Model of a Controlled Rectifier for Reactive Power Compensation |
B. R. Biswas, R. Das, M. A. Abedin and ABM. H. Rashid |
International Conference on Electrical and Computer Engineering (ICECE 2018), 20-22 December 2018, Dhaka, Bangladesh. |
8 |
2018 |
Design and Implementation of a FPGA Based Closed Loop Speed Controller for DC Motor using PWM Technique |
J. Barua and M. A. Abedin |
International Conference on Advancement in Electrical and Electronic Engineering (ICAEEE 2018), 22-24 November, 2018, Gazipur, Bangladesh. |
9 |
2018 |
Design and Implementation of a Microcontroller Based Forced Air Egg Incubator |
M. A. Kabir and M. A. Abedin |
International Conference on Advancement in Electrical and Electronic Engineering (ICAEEE 2018), 22-24 November, 2018, Gazipur, Bangladesh. |
10 |
2016 |
A Novel Low Buffered Optimized Solid State Drive Controller |
R. Das, B. R. Biswas, ABM H. Rashid and M. A. Abedin |
9th International Conference on Electrical and Computer Engineering (ICECE 2016), pp. 234 – 237, 20-22 December 2016, Dhaka, Bangladesh. |
11 |
2016 |
Implementation of a Three Phase Inverter for BLDC Motor Drive |
A. Mohammad, M. A. Abedin and M. Z. R. Khan |
9th International Conference on Electrical and Computer Engineering (ICECE 2016), pp. 337 – 340, 20-22 December 2016, Dhaka, Bangladesh. |
12 |
2016 |
Microcontroller Based Control System for Electric Vehicle |
A. Mohammad, M. A. Abedin and M. Z. R. Khan |
International Conference on Informatics, Electronics & Vision (ICIEV 2016), pp. 693-696, 13-14 May 2016, Dhaka, Bangladesh. |
13 |
2008 |
Fully Parallel Single and Two-stage Associative Memories for High Speed Pattern Matching |
M. A. Abedin, T. Koide and H. J. Mattausch |
5th International Conference on Electrical and Computer Engineering (ICECE 2008), pp. 291 – 296, 20-22 December 2008, Dhaka, Bangladesh. |
14 |
2007 |
Fully Parallel Associative Memory with Human Memory Type Learning Model |
M. A. Abedin, A. Ahmadi, T. Koide and H. J. Mattausch |
10th International Conference on Computer and Information Technology (ICCIT 2007), pp. 73 – 79, 27-29 December 2007, Dhaka, Bangladesh. |
15 |
2007 |
Hardware Realization of Two-Stage Pattern Matching System using Fully-Parallel Associative Memories |
M. A. Abedin, Y. Tanaka, S. Sakakibara, T. Koide and H. J. Mattausch |
The 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2007), pp. 32 – 37, 15-16 October 2007, Hokkaido, Japan. |
16 |
2007 |
A Fast Differential-Amplifier-Based Winner-Search Circuit for Fully Parallel Associative Memories |
Y. Tanaka, M. A. Abedin, S. Sakakibara, T. Koide and H. J. Mattausch |
The 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2007), pp. 38 – 41, 15-16 October 2007, Hokkaido, Japan. |
17 |
2007 |
Associative memory Design Realizing Reference-Pattern Recognition and Learning based on Short/Long-Term Storage Concept |
S. Sakakibara, M. A. Abedin, Y. Tanaka, H. J. Mattausch and T. Koide |
The 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2007), pp. 21–25, 15-16 October 2007, Hokkaido, Japan. |
18 |
2007 |
Developing a Reliable Learning Model for Cognitive Classification Tasks Using an Associative Memory |
A. Ahmadi, H. J. Mattausch, M. A. Abedin, T. Koide, Y. Shirakawa and A. Ritonga |
IEEE Symposium on Computational Intelligence in Image and Signal Processing (CIISP 2007), pp. 214 – 219, 1-5 April 2007, Hawaii, USA. |
19 |
2007 |
Mixed Analog-Digital Fully- Parallel Associative Memory with Differential Amplifier |
Y. Tanaka , M. A. Abedin, T. Koide and H. J. Mattausch |
Technical Report of IEICE, Vol. 106, No. 548, pp. 31 – 36, 7-9 March 2007, Okinawa, Japan. |
20 |
2007 |
Application of Fully Parallel Associative Memory in Two-Stage Pattern Matching |
M. A. Abedin, A. Ahmadi, Y. Tanaka, S. Sakakibara, T. Koide and H. J. Mattausch |
5th Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, pp. 124 – 125, 29-30 January 2007, Tokyo, Japan. |
21 |
2007 |
Functional-Memory Architectures for Information-Processing Systems |
H. J. Mattausch, T. Koide, M. A. Abedin and K Johguchi |
5th Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, pp. 46 – 49, 29-30 January 2007, Tokyo, Japan. |
22 |
2007 |
A Human-memory Based Learning Model and Hardware Prototyping in FPGA |
A. Ahmadi, M. A. Abedin, H. J. Mattausch, T. Koide, Y. Shirakawa and A. Ritonga |
5th Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, pp. 120 – 123, 29-30 January 2007, Tokyo, Japan. |
23 |
2006 |
Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search |
M. A. Abedin, Y. Tanaka, A. Ahmadi, T. Koide and H. J. Mattausch |
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2006), pp. 1311 – 1314, 4-7 December 2006, Singapore. |
24 |
2006 |
Nearest-Euclidean-Distance Search Associative Memory with Fully Parallel Mixed Digital-Analog Match Circuitry |
M. A. Abedin, Y. Tanaka, A. Ahmadi, T. Koide and H. J. Mattausch |
Extended abstract of the Int. Conf. on Solid State Devices and Materials (SSDM’2006), pp. 282 – 283, 12-15 September 2006, Pacific Yokohama, Japan. |
25 |
2006 |
Fully-Parallel Nearest Euclidean Distance Search Associative Memory Architecture |
M. A. Abedin, T. Koide and H. J. Mattausch |
International PhD Student Workshop on SOC (IPS’2006), pp. 75 – 78, 24-28 July 2006, Taipei, Taiwan. |
26 |
2006 |
A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA |
A. Ahmadi, M. A. Ritonga, M. A. Abedin, H. J. Mattausch and T. Koide |
IEEE World Congress on Computational Intelligence (WCCI’2006), pp. 2702 – 2708, 16-21 July 2006, Vancouver, BC, Canada. |
27 |
2006 |
Minimum Euclidean Distance Associative Memory Architecture with Fully-Parallel Search Capability |
M. A. Abedin, K. Kamimura, A. Ahmadi, T. Koide, and H. J. Mattausch |
The 13th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2006), pp. 350 – 354, 3-4 April 2006, Nagoya, Japan. |
28 |
2005 |
Fully-Parallel Associative Memory Architecture Realizing Minimum Euclidean Distance Search |
M. A. Abedin, K. Kamimura, A. Ahmadi, H. J. Mattausch, and T. Koide |
4th Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, pp. 58 – 59, 16th September 2005, Hiroshima, Japan. |
29 |
2005 |
Associative Memory Based Hardware Design for an OCR System and Prototyping with FPGA |
A. Ahmadi, M. A. Abedin, K. Kamimura, Y. Shirakawa, K. Takemura, H. J. Mattausch, and T. Koide |
4th Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, pp. 56 – 57, 16th September 2005, Hiroshima, Japan. |
30 |
2005 |
A Parallel Hardware Design for Parametric Active Contour Models |
A. Ahmadi, M. A. Abedin, H. J. Mattausch, and T. Koide |
IEEE International Conference on Advanced Video and Signal-Based Surveillance (AVSS 2005), pp. 609 – 613, 15-16 September 2005, Como, Italy. |
31 |
2005 |
An LSI hardware design for online character recognition using associative memory |
A. Ahmadi, Y. Shirakawa, M. A. Abedin, K. Takemura, K. Kamimura, H. J. Mattausch, and T. Koide |
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2005), pp. 464 – 467, 7-10 August 2005, Ohio, USA. |
32 |
2004 |
Real-Time Character Recognition System Using Associative Memory Based Hardware |
A. Ahmadi, Y. Shirakawa, M. A. Abedin, K. Takemura, K. Kamimura, H. J. Mattausch, and T. Koide |
3rd Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, pp. 40 – 41, 6th December 2004, Hiroshima, Japan. |
33 |
2002 |
Analytical Base Transit Time Model of a Bipolar Junction Transistor Considering Kirk Effect |
M. A. Abedin and M. M. S. Hassan |
International Conference on Electrical and Computer Engineering (ICECE), pp. 136 – 139, 26-28 December 2002, Dhaka, Bangladesh. |
34 |
2002 |
Analytical Base Transit Time Model of Uniformly Doped Base Bipolar Transistors Considering Kirk Effect |
M. A. Abedin and M. M. S. Hassan |
International Conference on Electrical Engineering (ICEE), pp. 93 – 100, 23-24 October 2002, Khulna, Bangladesh. |
35 |
2002 |
Modified UDP for Reliable Data Transmission Through a Lossy Communication Link |
M. S. Rahman, M. N. Ahsan and M. A. Abedin |
International Conference on Electrical Engineering (ICEE), pp. 191 – 196, 23-24 Oct 2002, Khulna, Bangladesh. |